module display(
    input clk_200,
    input [3:0] hex3,
    input [3:0] hex2,   
    input [3:0] hex1,
    input [3:0] hex0,
    input [3:0]display_en, //用两个信号H_display_en和V_display_en拼接成输入{H_display_en,V_display_en}
    output reg [3:0] an,
    output reg [7:0] sseg
    );
    
    reg [1:0] regN;
    reg [3:0] hex_in;
    reg dp;
    initial begin regN = 0;end
    always@(posedge clk_200)
        regN <= regN + 1;
                 
    always@*
        begin
            dp = 1'b0;
            case(regN)
                2'b00:
                    begin
                        an=4'b1110 | display_en;
                        hex_in=hex0;
                    end                            
                2'b01:
                    begin
                        an=4'b1101 | display_en;
                        hex_in=hex1;
                    end    
                2'b10:
                    begin
                        an=4'b1011 | display_en;
                        hex_in=hex2;
                    end    
                2'b11:
                    begin
                        an=4'b0111 | display_en;
                        hex_in=hex3;
                    end   
                default:
                    begin
                        an = 4'b1111;
                        hex_in = 4'b0000;
                    end                              
            endcase
        end
                 
    always @ *   
        begin
            case(hex_in)
              4'h0: sseg[7:1] = 7'b1111110;
                4'h1: sseg[7:1] = 7'b0110000;
                4'h2: sseg[7:1] = 7'b1101101;
                4'h3: sseg[7:1] = 7'b1111001;
                4'h4: sseg[7:1] = 7'b0110011;
                4'h5: sseg[7:1] = 7'b1011011;
                4'h6: sseg[7:1] = 7'b1011111;
                4'h7: sseg[7:1] = 7'b1110000;
                4'h8: sseg[7:1] = 7'b1111111;
                4'h9: sseg[7:1] = 7'b1111011;
                4'ha: sseg[7:1] = 7'b1110111;
                4'hb: sseg[7:1] = 7'b0011111;
                4'hc: sseg[7:1] = 7'b1001110;
                4'hd: sseg[7:1] = 7'b0111101;
                4'he: sseg[7:1] = 7'b1001111;
                default: sseg[7:1] = 7'b1000111;  //4'hf        
            endcase
        sseg[0]=dp;
    end
endmodule